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| ? 2001 microchip technology inc. advance information ds70025d-page 1 m DSPIC30F high performance cpu: ? c-compiler optimized instruction set architecture 94 base instructions - flexible addressing modes linear program memory addressing up to 4m x 24-bit linear data memory up to 64k bytes up to 144k bytes on-chip flash program mem- ory - 48k single word instructions (initially) up to 8k bytes on-chip data ram up to 4k bytes eeprom two 40-bit wide accumulators with optional satu- ration logic 16 x 16-bit working register array up to 30 mips operation: - dc - 120 mhz clock input - 4 mhz - 10 mhz osc./clock input with pll active (4x, 8x, 16x) 24-bit wide instructions, 16-bit wide data path dual address generation units enabling dual data fetch for dsp operations up to 32 interrupt sources 15 exception vectors (8 interrupts & 7 traps) - programmable priority levels for 8 interrupts - 3 cycle fixed latency; 1 ?fast? at 1 cycle 16 x 16 single cycle hardware fractional/integer multiplier single cycle multiply-accumulate (mac) opera- tion 40 stage barrel shifter peripheral features: high current sink/source i/o pins 25 ma/25 ma multiple external interrupt pins timer module: - five 16-bit timers/counters - 4 of the timers may be optionally configured as two 32-bit timer/counter 32 khz real-time clock support on timer1 capture input functions (16-bit, up to 8 pins) compare / pwm outputs functions (up to 8 pins) - 16-bit, max resolution 33.3 ns (t cy ) - dual compare mode available motor control pwm module quadrature encoder module data converter interface (dci), supports common audio codec protocols - including i 2 s, ac?97 3-wire spi ? modules (supports all 4 spi modes) i 2 c ? module (supports full multi - master / slave mode and 7-bit/10-bit addressing) addressable uart modules: supports interrupt on address bit and wake-up on start bit detection can bus modules as many as 54 programmable digital i/o pins - some with interrupt on change advanced analog features: 10-bit analog-to-digital converters (a/d) with: - 16 input channels, typically - 500 ksps conversion rate - conversion available during sleep 12-bit analog-to-digital converters (a/d) with: - 16 input channels, typically - 100 ksps conversion rate - conversion available during sleep programmable low voltage detection (lvd) - supports interrupt on low voltage detection programmable brown-out reset generation special microcontroller features: power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation fail safe clock monitor operation programmable code protection selectable power management modes - sleep mode, idle mode, slowdown mode dspic ? high-performance 16-bit digital signal controller family overview
DSPIC30F ds70025d-page 2 advance information ? 2001 microchip technology inc. selectable oscillator options, including: - 4x/8x/16x phase lock loop (of primary oscillator) - secondary oscillator (32 khz) clock input (timer1) - high speed internal rc oscillator in-circuit serial programming ? (icsp ? ) via 3 pins and power/ground cmos technology: low-power, high-speed flash technology fully static design wide operating voltage range (2.5v to 5.5v) industrial and extended temperature ranges low power consumption packaging: 100-pin tqfp 64-pin tqfp 40-pin dip, 44-pin tqfp 28-pin dip (300 mil.), 28-pin ssop 1.0 cpu core architectural description the DSPIC30F digital signal controller is a modified harvard architecture core with a 16-bit datapath and a 24-bit wide instruction memory. the DSPIC30F core seamlessly integrates the superior control attributes of a 16-bit mcu and the computation power of a dsp. the DSPIC30F instruction set adds many enhance- ments to the previous picmicro microcontroller (mcu) instruction sets, while maintaining an easy migration path from these picmicro mcu platforms. 1.1 core overview the core has a 24-bit instruction word, with a variable length opcode field. the pc (program counter) is 23 bits wide (with the ls-bit always clear, see figure 1-3 and table 1-1), addressing up to 4m long words (24 bits). an pic18c-like instruction prefetch mechanism is used to help maintain throughput. deeper levels of pipelining have been intentionally avoided to maintain good real-time performance. unconditional overhead free program loop constructs are supported using the do and repeat instructions, both of which are inter- ruptable at any point. the working register array is comprised of 16 x 16-bit registers, each of which can act as data, address or off- set registers. one working register (w15) operates as the software stack pointer for interrupts and calls. the data space is 32k words of word or byte address- able space, which is split into two blocks referred to as x and y data memory. each block has its own indepen- dent address generation unit (agu). most instructions operate solely through the x memory agu which will make it appear as one linear space encompassing all data space (x and y). the mac class of dsp instruc- tions will operate through both the x and y agus, split- ting the data address space into two parts (see section 1.2.1). the x and y data space boundary is arbitrary and defined through the address decode of each memory array. the upper 32k bytes of data space memory can option- ally be mapped into program space at any 16k pro- gram word boundary defined by the 8-bit data space program page (dsppag) register. this lets any instruction access program space as if it were data space (other than the additional access cycle it con- sumes), plus it allows external ram hooked onto the external program space bus to be mapped into data space, effectively providing an external data space path. overhead free circular buffers (modulo addressing) are supported in both x and y address spaces. they are intended to remove the loop overhead for dsp algo- rithms, but x modulo addressing can be universally applied using any instructions. the x agu also supports bit reverse addressing to greatly simplify input or output data reordering for radix- 2 fft algorithms. the instruction set architecture (isa) has been signifi- cantly enhanced beyond that of the pic18c, but main- tains an acceptable level of backward compatibility. all pic18c instructions and addressing modes are sup- ported either directly or through simple macros. many of the isa enhancements have been driven by compiler efficiency needs (see section 1.1.1). the core supports inherent (no operand), relative, lit- eral, memory direct and 3 groups of addressing modes (mode1, mode2 and mode3) for register direct and register indirect modes. there are 11 addressing modes in total, plus some special varients for dsp instruction. instructions are associated with predefined addressing modes depending upon their functional requirements. please refer to the instruction set description document [ds70026n_c] for more details. for most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, 3 operand instructions can be supported, allow- ing a+b=c operations to be executed in a single cycle. ? 2001 microchip technology inc. advance information ds70025d-page 3 DSPIC30F a dsp engine has been included to significantly enhance the core arithmetic capability and throughput. it features a high speed 16-bit by 16-bit multiplier, a 40- bit alu, two 40-bit saturating accumulators and a 40- bit bi-directional barrel shifter. the barrel shifter is capable of shifting a 40-bit value up to 15 bits right or up to 16 bits left in a single cycle. the dsp instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. the mac class of instructions can concurrently fetch two data operands from memory while multiplying two w registers and accumulating the results. this requires that the data space be split for these instructions and linear for all others. this is achieved in a transparent and flexible manner through dedicating certain working registers to each address space for the mac class of instructions. the core features a sophisticated interrupt structure with 15 individually prioritized vectors. the interrupts and exceptions consist of reset, 7 traps and 8 inter- rupts. up to 32 interrupt sources are supported. one interrupt level may be selected (typically the highest one) to execute as a fast (1 cycle entry, 1 cycle exit) interrupt. this function is actually an extension of the logic required to allow a repeat instruction loop to be interrupted, which can significantly reduce latency in some application. a block diagram of the core is shown in figure 1-1. 1.1.1 compiler driven enhancements in addition to dsp performance requirements, the core architecture was strongly influenced by recommenda- tions which would lead to a more efficient (code size and speed) c compiler. 1. for most instructions, the core is capable of exe- cuting a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, 3 operand instructions can be supported, allowing a+b=c operations to be executed in a single cycle. 2. instruction addressing modes are extremely flexible to meet compiler needs. 3. the working register array is comprised of 16 x 16-bit registers, each of which can act as data, address or offset registers. one working register (w15) operates as the software stack pointer for interrupts and calls. 4. linear indirect access of all data space is possi- ble, plus the memory direct address range has been extended to 8k bytes. this, together with the addition of 16-bit direct address load and store instructions, has provided a contiguous linear addressing space. 5. linear indirect access of 32k word (64k byte) pages within program space is possible using any working register via new table read and write instructions. 6. part of data space can be mapped into program space, allowing constant data to be accessed as if it were in data space. 1.1.2 instruction fetch mechanism a one-stage pre-fetching mechanism accesses each instruction a cycle ahead to maximize available execu- tion time. most instructions execute in a single cycle. exceptions are: 1. flow control instructions (such as program branches, calls, returns) take 2 cycles since the ir (instruction register) and pre-fetch buffer must be flushed and refilled. 2. instructions where one operand is to be fetched from program space (using any method). these operations consume 2 cycles (with the notable exception of the mac class of dsp instructions executed within a repeat loop which executes in 1 cycle). most instructions access data as required during instruction execution. instructions which utilize the mul- tiplier array must have data available at the beginning of the instruction cycle. consequently, this data must be prefetched, usually by the preceding instruction, resulting in a simple out of order data processing model. a programmer model diagram is shown in figure 1-2. DSPIC30F ds70025d-page 4 advance information ? 2001 microchip technology inc. figure 1-1: cpu core block diagram sign extend 22 address decode x data latch program memroy bus data latch up to 4 m words address latch 24 24 22 table & data space 22 instruction decode alu<8/16> 16 db<16:0> pclatu pcu pch pcl status 8/16 16 x 16 multiplier acca accb barrel 40-bit add/sub operand latches 22 address decode y data latch 16 data ram loop control logic w array (16 x 16-bit regs) y data data ram x data 16 y address x address program data ea address generator table data byte/word instruction register instruction latch early partial instruction decode program memory 24-bit wide x agu y agu x address select 32 w15 / stack ptr. stack logic control program counter 16 pop/push pc register r/w 16 6 pc shifter round logic 32 zero backfill 16 16 40 40 40 40 40 16 32 16 16 inst. type 32 16 page registers do registers r/w 16 16 16 data memory bus (peripherals) 16 16 (external memory) (see note) (see note) note : the ram is logically separated in two sections for dsp operations to allow fetching of two variables in one cycle. however, for all mcu operations, the ram appears as one contiguous space. ? 2001 microchip technology inc. advance information ds70025d-page 5 DSPIC30F figure 1-2: programmer model diagram novz c tabpag pc0 7 0 d0 d15 program counter data table page address status register working/ address registers dsp operand registers wreg0 wreg1 wreg2 wreg3 wreg4 wreg5 wreg6 wreg7 wreg8 wreg9 wreg10 wreg11 wreg12 wreg13 frame pointer / wreg14 stack ptr / wreg15* dsp address registers ad39 ad0 ad31 dsp accumulators acca accb dsppag 7 0 data space prog page address dc 0 oa ob sa sb rcount 15 0 repeat loop counter dcount 15 0 do loop counter dostart 21 0 do loop start address doend do loop end address da ra splim* stack pointer limit ad15 21 0 srl * w15[0] & splim[0] always = 0 sz w15 & splim not shadowed fast interrupt shadow nested do shadow repeat interrupt shadow 0 0 oab sab pc22 DSPIC30F ds70025d-page 6 advance information ? 2001 microchip technology inc. figure 1-3: memory map diagram pc<23:0> reset user memory space 24 0x000000 0x7ffffe 0x00001e ext. osc. fail trap 0x000002 0x000020 user flash program memory 0x010000 0x00fffe or external memory stack error trap address error trap arithmetic warn. trap software trap reserved reserved priority interrupt 7 priority interrupt 6 priority interrupt 5 priority interrupt 4 priority interrupt 3 priority interrupt 2 priority interrupt 1 priority interrupt 0 (32k instructions) unused - read ? 0 ? s program memory space 0x1ffe 8k byte access space 0x2ffe 0x3000 0xfffe x data ram (x) y data ram (y) ls byte address byte select mux ea[0] d[15:0] 16-bits lsb msb ms byte address 0x0001 0x1fff 0x2fff 0x3001 0xffff 0x3fff 0x3ffe x data unused (x) 0x8001 0x8000 optionally transparent into program memory data memory space [ example] [ example] 0x0000 ? 2001 microchip technology inc. advance information ds70025d-page 7 DSPIC30F 1.2 data address space the core features one program space and two data spaces. the data spaces can be considered either sep- arately (for some dsp instructions) or together as one linear address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. 1.2.1 data spaces the x agu is used by all instructions and supports all addressing modes. it also supports modulo and bit reversed addressing for any instruction (subject to addressing mode restrictions). the x data path is the return data path for all single data space access instructions. the y agu and data path are used in concert with the x agu by the mac class of instructions to provide two concurrent data read paths. no writes occur across the y-bus. this class of instructions dedicate two w regis- ter pointers, w6 and w7, to always operate through the y agu and address y data space independently from x data space. note that during accumulator write to data space, the data address space is considered combined x and y, so the write will occur across the x- bus. consequently, it can be to any address irrespec- tive of where the ea is directed. the y agu only supports post modification addressing modes associated with the mac class of instructions. it also supports modulo addressing for automated circu- lar buffers. of course, all other instructions can access the y data address space through the x agu when it is regarded as part of the composite linear space. the boundary between the x and y data spaces is arbi- trary and is defined by the memory address decode only (the cpu has no knowledge of the physical loca- tion of x or y memory). the boundary is not user pro- gramable, but may change from variant to varient. obviously, to present a linear data space to the mcu instructions, the address spaces of x and y data spaces must be contiguous, but this is not an architec- tural necessity. all effective addresses (ea) are 16 bits wide and point to bytes within the data space to facilitate backward compatibility with the pic18c. consequently, the data space address range is 64k bytes or 32k words. 1.2.2 data space width the core data width is 16 bits. all internal registers and data space memory are organized as 16 bits wide (some cpu registers are not 16 bits wide). data space memory is organized in byte addressable, 16-bit wide blocks. 1.2.3 data alignment to help maintain pic18c backward compatibility and improve data space memory usage efficiency, the dsc core supports both word and byte operations, by way of an instruction attribute. data is aligned in data mem- ory and registers as words, but all data space eas resolve to bytes (see figure 1-4). data byte reads will read the complete word which contains the byte, using the ls-bit of any ea to determine which byte to select. the selected byte is placed onto the ls-byte of the x data path (no byte accesses are possible from the y data path as the mac class of instruction can only fetch words). that is, data memory and registers are orga- nized as two parallel byte wide entities with shared (word) address decode but separate write lines. data byte writes will only write to the corresponding side of the array or register which matches the byte address. for word accesses, the ls-bit of the ea is ignored (don ? t care). as a consequence of this byte accessibility, all effective address calculations (including those generated by the dsp operations which are restricted to word size) are automatically scaled to step through word aligned memory. for example, the core recognizes that post modified register indirect addressing mode, [ws]+=1, will result in a value of ws+1 for byte operations and ws+2 for word operations. all word accesses must be aligned (to an even address). misaligned word data fetches are not sup- ported, so care must therefore be taken when mixing byte and word operations or translating from pic18c code. should a misaligned read or write be attempted, an address fault trap will be forced. figure 1-4: data alignment all byte loads into any w register are loaded into the ls-byte. the ms-byte is not modified. note: byte operations use the 16-bit alu and can produce results in excess of 8 bits. how- ever, to maintain pic18c backwards com- patibility, the alu result from all byte operations is written back as a byte (i.e., ms byte not modified), and the status regis- ter is updated based only upon the state of the ls-byte of the result. 15 8 7 0 0001 0003 0005 0000 0002 0004 byte1 byte 0 byte3 byte 2 byte5 byte 4 ls byte ms byte DSPIC30F ds70025d-page 8 advance information ? 2001 microchip technology inc. a sign extend (se) instruction is provided to allow users to translate 8-bit signed data to16-bit signed val- ues. alternatively, for 16-bit unsigned data, users can clear the ms-byte of any w register though executing a clr.b instruction on the appropriate address. (all cpu core registers are memory mapped into data space). although most instructions are capable of operating on word or byte data sizes, it should be noted that the dsp and some other new instructions operate on words only. 1.3 program address space the program address space is 4m long words. it is addressable by a 22-bit value from either the pc, table instruction ea or data space ea when program space is mapped into data space as defined by table 1-1. note that the program space address is incremented by two between successive program words in order to provide compatibility with data space addressing. con- sequently, the ls-bit of the program space address is always 0, resulting in 22 bits of address. program space data accesses use the ls-bit of the program space address as a byte select (same as data space) table 1-1: program space address construction the program memory width is 24 bits (long word). to support data storage and flash programming, the array must support both word wide access from bits 0- 15 and byte wide access from bits 16-23. see figure 1-5 and figure 1-6 for program space addressing conventions. figure 1-5: instruction fetch example access type program space address [22:16] [15] [14:1] [0] instruction access pc[22:1] 0 tblrd/tblwt tabpag[6: 0] data ea [15:0] ds window into ps dsppag[7:0] data ea [14:0] pc22 pc0 program counter 0 0x000000 0x7ffffe 24-bits prefetch instruction 22 +1 (see note) note : increment of pc<22:1> is equivalent to pc<22:0>+2 24 22 user space instruction register ? 2001 microchip technology inc. advance information ds70025d-page 9 DSPIC30F figure 1-6: program space memory map user program space 1.4 dsp engine the dsp engine is a block of hardware which is fed data from the w register array, but contains its own specialized result registers. it is controlled from the same single issue instruction decoder that directs the mcu alu. in addition, all operand effective addresses are generated in the w register array. some dsp instructions (e.g., ed and edac instructions) utilize both the dsp engine and the mcu alu resources concurrently. the dsp engine consists of a high speed 16-bit x 16-bit multiplier, a barrel shifter and a 40-bit adder/subtractor with two target registers, round and saturation logic. data input to the dsp engine is derived from: 1. directly the w array (registers w0, w1, w2 or w3) for the mac class of instructions (mac, msa, mpy, mpyn, sqr, sqrac, clrac and movsac) and mcu multiply instructions. 2. the x-bus for all other dsp instructions 3. the x-bus for all mcu instructions which use the barrel shifter data output from the dsp engine is written to: 1. the target accumulator, as defined by the dsp instruction being executed 2. the x-bus for mac, msa, clrac and movsac accumulator writes where the ea is derived from w9 only (mpy, mpyn, sqr and sqrac do not offer an accumulator write option) 3. the x-bus for all mcu instructions which use the barrel shifter 4. the w array for some mcu multiply instructions. the dsp engine also has the capability to perform inherent accumulator to accumulator operations which require no additional data. these instructions are addab, subab and negac. a block diagram of the dsp engine is shown in figure 1-7. 0x000000 reset 0x000002 ext. osc. fail trap 0x000004 stack error trap 0x000006 address error trap 0x00000a arithmetic warn. trap 0x00000c software trap 0x00000e reserved 0x00000f reserved 0x000010 priority interrupt 7 0x000012 priority interrupt 6 0x000014 priority interrupt 5 0x000016 priority interrupt 4 0x000018 priority interrupt 3 0x00001a priority interrupt 2 0x00001c priority interrupt 1 0x00001e priority interrupt 0 0x000020 user program space 0x7ffffe DSPIC30F ds70025d-page 10 advance information ? 2001 microchip technology inc. figure 1-7: dsp engine block diagram zero-backfill sign extend barrel shifter 40-bit accumulator a 40-bit accumulator b round logic x data bus multiplier/scaler to/from w array adder saturate operand latches enable 16-bit saturate negate 32 32 32 16 16 16 ? 2001 microchip technology inc. advance information ds70025d-page 11 DSPIC30F 2.0 development tools support microchip is offering a comprehensive package of development tools and libraries to support the dspic architecture. in addition, the company is partnering with many third party tools manufacturers for additional dspic support. the microchip tools will include: mplab ? 6.00 integrated development environ- ment (ide) dspic language suite including mplab c30 c compiler, assembler, linker and librarian mplab sim software simulator mplab ice 4000 in-circuit emulator mplab icd 2 in-circuit debugger pro mate ? ii universal device programmer picstart ? plus development programmer 2.1 mplab v6.00 integrated development environment software the mplab integrated development environment is available at no cost. the ide gives users the flexibility to edit, compile and emulate all from a single user inter- face. engineers can design and develop code for the dspic in the same design environment that they have used for picmicro microcontrollers. the mplab ide is a 32-bit windows ? based applica- tion. it provides many advanced features for the critical engineer in a modern, easy to use interface. mplab integrates: full featured, color coded text editor easy to use project manager with visual display source level debugging enhanced source level debugging for ? c ? (structures, automatic variables, and so on) customizable toolbar and key mapping dynamic status bar displays processor condition at a glance context sensitive, interactive on-line help integrated mplab sim instruction simulator user interface for pro mate ii and picstart plus device programmers (sold separately) user interface for mplab ice 4000 in-circuit emulator (sold separately) user interface for mplab icd 2 in-circuit debug- ger the mplab ide allows the engineer to: edit your source files in either assembly or ? c ? one-touch compile and download to dspic pro- gram memory on emulator or simulator. updates all project information. debug using: - source files - machine code - mixed-mode source and machine code the ability to use the mplab ide with multiple devel- opment and debugging targets allows users to easily switch from the cost-effective simulator to a full-fea- tured emulator with minimal retraining. 2.2 dspic language suite the microchip technology mplab c30 c compiler is a fully ansi compliant product with standard libraries for the dspic architecture. it is highly optimizing and takes advantage of many dspic architecture specific fea- tures to provide efficient software code generation. mplab c30 also provides extensions that allow for excellent support of the hardware such as interrupts and peripherals. it is fully integrated with the mplab ide for high level, source debugging. 16-bit native data types efficient use of register-based, 3-operand instruc- tions complex addressing modes efficient multi-bit shift operations efficient signed/unsigned comparisons mplab c30 comes complete with its own in assem- bler, linker and librarian. these allow the user to write mixed-mode c and assembly programs and link the resulting object files into a single executable file. the compiler is sold separately. the assembler, linker and librarian are available for free with mplab. DSPIC30F ds70025d-page 12 advance information ? 2001 microchip technology inc. 2.3 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the dspic on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execution can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c30 compiler and assem- bler. the software simulator offers the flexibility to develop and debug code outside of the laboratory envi- ronment, making it an excellent multi-project software development tool. 2.4 mplab ice 4000 in-circuit emulator the mplab ice 4000 in-circuit emulator is intended to provide the product development engineer with a complete hardware design tool for the dspic. software control of the emulator is provided by mplab, allowing editing, building, downloading and source debugging from a single environment. the mplab ice 4000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the mplab ice 4000 supports the extended, high end picmicro microcontrollers, the 18cxxx and 18fxxx devices, as well as the dspic family of digital signal controllers. the modular architecture of the mplab ice in-circuit emulator allows expansion to support new devices. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. full-speed emulation, up to 50mhz bus speed, or 200mhz external clock speed low-voltage emulation down to 1.8 volts configured with 2mb program emulation memory, additional modular memory up to 16mb 32k x 136-bit wide trace memory unlimited software breakpoints complex break, trace and trigger logic multi-level trigger up to 4 levels filter trigger functions to trace specific event 16-bit pass counter for triggering on sequential events 16-bit delay counter 48-bit time stamp stopwatch feature time between events statistical performance analysis code coverage analysis usb and parallel printer port pc connection 2.5 mplab icd 2 in-circuit debugger microchip ? s in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the picmicro and dspic flash devices the mplab icd utilizes the in-circuit debugging capa- bility built into the various devices. this feature, along with microchip ? s in-circuit serial programming ? proto- col, offers cost-effective in-circuit debugging from the graphical user interface of mplab. this enables a designer to develop and debug source code by watch- ing variables, single-stepping and setting break points. running at full speed enables testing hardware in real- time. full speed operation to the range of the device serial or usb pc connector serial interface externally powered usb powered from pc interface low-noise power (vpp and vdd) for use with analog and other noise sensitive applications operation down to 2.0v can be used as an icd or in-expensive serial pro- grammer modular application connector as mplab-icd limited number of breakpoints ? smart watch ? variable windows some chip resources required (ram, program memory and 2 pins) ? 2001 microchip technology inc. advance information ds70025d-page 13 DSPIC30F 2.6 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has programma- ble vdd and vpp supplies, which allow it to verify pro- grammed memory at vdd min and vdd max for maximum reliability when programming requiring this capability. it has an lcd display for instructions and error messages, keys to enter commands. inter- changeable socket modules all package types. in stand-alone mode, the pro mate ii device pro- grammer can read, verify, or program picmicro devices. it can also set code protection in this mode. runs under mplab field upgradable firmware dos command line interface for production host, safe, and ? stand alone ? operation automatic downloading of object file sqtp serialization adds unique serial number to each device programmed in-circuit serial programming kit (sold separately) interchangeable socket modules supports all package options (sold separately) 3.0 exception processing the dspic has 15 exception sources plus reset, which are arbitrated based on a priority scheme. exceptions are either reset, fixed priority non- maskable traps or user programmable priority inter- rupts. the exception priority table is shown in figure 3- 1. the interrupts are enabled, prioritized, and con- trolled using centralized special function registers. all interrupt sources can be user assigned to one of 8 priority levels, 0 through 7. each level is associated with an interrupt vector as shown in figure 3-1. level 6 and 0 represent the highest and lowest maskable prior- ities respectively. level 7 interrupts are non-maskable and are handled slightly differently from all other inter- rupts. certain interrupts have specialized control bits for fea- tures like edge or level triggered interrupts, interrupt on change, etc. control of these features remains within the peripheral module which generates the interrupt. 3.1 interrupt priority the interrupt priority bits for each individual interrupt are located in bits within the interrupt priority control registers (intcon). these bits define the priority level assigned to a particular interrupt. multiple interrupts can be assigned the same priority. once in the interrupt service routine (isr) for a partic- ular priority level, the interrupt can be determined by polling the interrupt flag bits. each interrupt priority has a corresponding interrupt vector. when an interrupt is serviced, the pc is loaded with the interrupt vector that corresponds to the priority level of that interrupt. there are 8 different interrupt vectors (see figure 3-1). 3.1.1 cpu priority register the cpu priority register is used to indicate the current priority of all pending interrupts and traps. the initial (reset) state of the cpu priority register is 0xffff. it contains one bit for each interrupt level 0 through 7 and trap priority level 8 through 14. it also contains one bit for reset. when an interrupt or trap is being serviced, the priority status bit associated with the interrupt is cleared in this register. this register can also be used to disable higher priority interrupts than the one currently being serviced. the global interrupt enable (gie) bit will disable all interrupt levels 0 through 6 when clear. exceptions greater than priority level 6 are non-maskable so they cannot be disabled in software. DSPIC30F ds70025d-page 14 advance information ? 2001 microchip technology inc. 3.2 exception sequence all interrupt event flags are sampled simultaneously and at a specific cpu clock phase. a pending interrupt indicated by the flag bit being equal to a ? 1 ? will cause the interrupt to occur. when an interrupt is latched, the interrupt priority bits associated with a pending flag are sampled in the next clock cycle before entering the isr. the sampling sequence is needed to determine if more than one interrupt flag, with different priorities, have been simultaneously latched. each of the interrupt sta- tus bits is arbitrated simultaneously. each of the pending interrupts has an associated prior- ity. the status of the pending interrupt is presented on one bit of an 8-bit interrupt request (irq) bus corre- sponding to one of 8 priorities. each bit on the request bus indicates to the cpu that at least one interrupt of priority ? n ? is present. if the irq bits sampled indicate a priority lower than or equal to the current cpu priority, then no interrupt sequence will occur. when all higher (priority) status bits are set as a result of the termination of their respec- tive isr ? s, then the isr of the pending status bit will be serviced. when an interrupt is serviced, the return address is pushed onto the stack together with the least significant byte of the status register (sr) as shown in figure 3-1. working register 15 is used as the implied stack pointer. figure 3-1: interrupt stack frame if interrupt nesting is disabled, subsequent interrupts of priority level 0 through 6 are prevented from causing a further exception sequence. however, interrupts con- tinue to be arbitrated and the cpu priority register con- tinues to be updated to reflect all subsequent interrupts which become pending. individual interrupt flag bits within the ifs (interrupt flag status) register(s) are set regardless of the status of the gie and the individual interrupt priority bits. the gie bit is also cleared on reset. note that traps and priority 7 interrupts are not disabled by the gie bit and are always enabled. if interrupt nesting is enabled, subsequent interrupts will be arbitrated and will clear the cpu priority register bits accordingly. should any of these be of a higher pri- ority than that currently being serviced, an interrupt at that level will be initiated. note: traps and priority 7 interrupts are always nestable. 3.2.1 interrupt/trap/reset vectors interrupt, trap and reset vectors are automatically loaded into the pc when servicing an interrupt, trap or following a reset. the vectors are contained in loca- tions 0x000000 through 0x00001f of program memory. these locations contain 24-bit addresses, and in order to preserve robustness, an address error trap will take place should the pc attempt to fetch any of these words during normal execution. this prevents execu- tion of random data. table 3-1: exception vector table traps can be considered as non-maskable, nestable interrupts which adhere to a predefined priority as shown in table 3-1. they are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. the software traps also provide a means to emulate new or unsupported instructions. note: if the user does not intend to take corrective action in the event of a trap error condition, these vectors must be loaded with the reset vector address. note that many of these trap conditions can only be detected when they happen. consequently, the ques- tionable instruction is allowed to complete prior to trap exception processing. if the user chooses to recover from the error, the result of the erroneous action which caused the trap may therefore have to be corrected. ? 2001 microchip technology inc. advance information ds70025d-page 15 DSPIC30F 3.2.1.1 reset sources in addition to external and power-on resets, there are three sources of error conditions which will ? trap ? to the reset vector. the possibility of recovery from these con- ditions is remote, so a hardware reset is the most robust course of action. watchdog time-out: the windowed watchdog has been reset too early or has timed out, indicating that the processor is no longer executing the correct flow of code. illegal instruction trap: the dspic 8-bit opcode field must be fully decoded. attempted execution of any unused slots will result in an illegal instruction trap. note that a fetch of an illegal instruction will not result in an illegal instruction trap if that instruction is flushed prior to execution due to a flow change. brown-out detect: a momentary dip in the power supply to the device has been detected which may result in malfunction. 3.2.1.2 trap sources the following traps are provided with increasing prior- ity. however, as all traps are nestable, priority has little effect. software trap: execution of a trap opcode will cause an inter- rupt. arithmetic error trap: the arithmetic error trap will execute under the following three circumstances. it is assumed that the dsp engine configuration will be consistent within an application, so polling flags to determine the error condition should not be necessary. 1. should an attempt be made to divide by zero, the divide operation will be aborted on a cycle boundary and the trap taken. 2. if enabled, an arithmetic error trap will be taken when an arithmetic operation on either accumu- lator a or b causes an overflow from bit 31 and the accumulator guard bits are unutilized. 3. if enabled, an arithmetic error trap will be taken when an arithmetic operation on either accumu- lator a or b causes a catastrophic overflow from bit 39 and all saturation is disabled. address error trap: this trap will be initiated when any of the following circumstances occurs: 1. a misaligned data word fetch is attempted 2. a data fetch from unimplemented data address space is attempted 3. a program fetch from unimplemented user pro- gram address space is attempted 4. a program fetch from vector address space is attempted 5. a read (for address) of an uninitialized w regis- ter is attempted. stack error trap this trap will be initiated under the following con- ditions: 1. the stack pointer is loaded with a value which is greater than the (user programmable) limit value written into the splim register (stack overflow). 2. the stack pointer is loaded with a value which is less than 0x0200 (simple stack underflow). oscillator fail trap: this trap will be initiated should the external oscil- lator fail and operation become reliant on an inter- nal rc backup. it is conceivable that multiple traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). in such a case, the fixed priority shown in figure 3-1 will be implemented which may require the user to check if other traps are pending in order to completely correct the fault. DSPIC30F ds70025d-page 16 advance information ? 2001 microchip technology inc. 4.0 resets the DSPIC30Fxxx differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset (during normal operation) e) programmable brown-out reset (pbor) f) reset instruction most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ? reset ? state on power-on reset, mclr , wdt reset, brown- out reset, mclr reset during sleep and by the reset instruction. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal oper- ation. status bits from the reset condition register, are set or cleared differently in different reset situations. these bits are used in software to determine the nature of the reset. a simplified block diagram of the on-chip reset circuit is shown in figure 4-1. the DSPIC30F devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. a wdt reset does not drive mclr pin low. figure 4-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd v dd rise detect osd/por timer wdt time-out power-on reset osd osc.stability detection por timer chip_reset 11-bit ripple counter reset enable oscillator stability detect enable por timer sleep note 1: this is a separate oscillator from the rc oscillator of the clki pin. brown-out reset boren reset instruction wdt module oscillator source ? 2001 microchip technology inc. advance information ds70025d-page 17 DSPIC30F 5.0 low voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application soft- ware can do "housekeeping tasks" before the device voltage exits the valid operating range. this can be done using the low voltage detect (lvd) module. this module contains software programmable circuitry, where a device voltage trip point can be specified (internal reference voltage). when the voltage of the device becomes lower than the specified point, an interrupt flag is set. if the lvd interrupt is enabled, the program execution will take a level 7 (interrupt) excep- tion and take appropriate action. the low voltage detect circuitry is completely under software control. this allows the circuitry to be "turned off" by the software, which minimizes the current con- sumption for the device. 6.0 dsc peripherals the digital signal controller (dsc) family of 16-bit mcu devices will provide the integrated functionality of many peripheral functions. the initial library of func- tions that will be utilized (one or more) on the dsc devices are as follows: 10-bit high speed a/d converter 12-bit high resolution a/d converter general purpose 16-bit timers watchdog timer module motor control pwm module quadrature encoder module input capture module output compare/ pwm module serial peripheral interface (spi ? ) module uart module i 2 c ? module controller area network (can) module i/o pins 6.1 a/d modules there will be 2 versions of a/d converters available for DSPIC30F family of devices. there is a 10-bit high speed a/d module and a 12-bit high resolution a/d module. 6.1.1 10-bit a/d features 10-bit resolution uni-polar differential inputs up to 16 input channels selectable reference inputs 1 lsb max dnl 2 lsb max inl up to four on-chip sample and hold amplifiers single supply operation: 2.7v - 5.5v 500ksps sampling rate at 5v ability to convert while the device sleeps low power cmos technology 5na typical standby current, 2a max 2.5 ma typical active current at 5v 6.1.2 12-bit a/d features 12-bit resolution uni-polar differential inputs up to 16 input channels selectable reference inputs 1 lsb max dnl 2 lsb max inl up to four on-chip sample and hold amplifiers single supply operation: 2.7v - 5.5v 100ksps sampling rate at 2.7v ability to convert while the device sleeps low power cmos technology 5na typical standby current, 2a max 2.5 ma typical active current at 5v DSPIC30F ds70025d-page 18 advance information ? 2001 microchip technology inc. 6.1.3 applications dc brushless motor control sr motor control ac induction motor control remote sensors sensor interface process control data acquisition 6.1.4 description the a/d modules provide up to 16 analog inputs with both single ended and differential inputs. these mod- ules offer on-board sample and hold circuitry. to minimize control loop errors due to finite update times (conversion plus computations), a high speed low latency adc is required. in addition, several hardware features have been added to the peripheral interface to improve real-time performance in a typical dsp based application. 3. result alignment options 4. automated sampling 5. dual port data buffer 6. external conversion start control the block diagram of the a/d module is shown in figure 6-1. ? 2001 microchip technology inc. advance information ds70025d-page 19 DSPIC30F figure 6-1: functional block diagram s/h + - 10-bit result conversion logic v ref + av ss av dd adc data format 16-word, 10-bit dual port ram bus interface an12 0000 0101 0111 1001 1101 1110 1111 1100 0001 0010 0011 0100 0110 1000 1010 1011 an13 an14 an15 an8 an9 an10 an11 an4 an5 an6 an7 an0 an1 an2 an3 cha chb chc ch0 chc10 chc4 chc11 chc5 chcg chb8 chb2 chb9 chb3 chbg cha6 cha0 cha7 cha1 chag ch0r ch0g v ref - sample / sequence control sample cha,chb, chc,ch0 input mux control input switches s/h + - s/h + - s/h + - DSPIC30F ds70025d-page 20 advance information ? 2001 microchip technology inc. 6.2 general purpose timer the general purpose (gp) timer module provides the time base elements for input capture, output com- pare/pwm and can be configured for a real-time clock operation as well as various timer/counter modes. figure 6-2 and figure 6-3 depict the simplified block diagrams of the two gp timer modules. the gp timer module consists of one 16-bit timer and one 32-bit timer, (which can be configured as two 16-bit timers), with selectable operating modes. these timers will be utilized by other dspic peripheral modules such as: input capture output compare real-time clock figure 6-2: 16-bit timer module simplified block diagram figure 6-3: 16-, 32-bit timer module simplified block diagram t cy prescaler and sync. logic timer1 register period1 register t1osci t1osco rtc t1cki/gate1 1 0 tmr1cs (optional) oscillator (optional) note 1: timer2 and timer3 can be configured for 32-bit timer/counter mode. t2cki/gate2 1 0 tmr2cs prescaler and sync. logic timer2 register period2 register t3cki/gate3 1 0 tmr3cs prescaler and sync. logic timer3 register period3 register (1) t cy t cy ? 2001 microchip technology inc. advance information ds70025d-page 21 DSPIC30F 6.3 watchdog timer module this is the description of watchdog timer (wdt) for the DSPIC30F family. 6.3.1 overview the primary function of the watchdog timer (wdt) is to reset the processor in the event of a software mal- function. the wdt is a free running timer which runs off an on-chip rc oscillator, requiring no external compo- nent. therefore, the wdt timer will continue to operate even if the main processor clock (e.g., the crystal oscil- lator) fails. 6.3.2 enabling and disabling the wdt the watchdog timer can be ? enabled ? or ? disabled ? only through a configuration bit (wdten) in the config- uration register. wdten=1 enables the watchdog timer. the enabling is done when programming the device. by default, after chip-erase, wdten bit =1. any device programmer capable of programming dspic devices (such as microchip ? s pro mate ? ii and picstart ? plus pro- grammers) allows programming of this and other con- figuration bits to the desired state. if enabled, the wdt will increment until it overflows or ? times out ? . a wdt time-out will force a device reset (except during sleep). to prevent a wdt time-out, the user must clear the watchdog timer using a clr- wdt instruction. if a wdt times out during sleep, the device will wake up. the status bit will be cleared ( ? 0 ? ) to indicate a wake-up resulting from wdt time-out 6.4 motor control pwm module this module simplifies the task of generating multiple, synchronized pulse width modulated (pwm) outputs. in particular, the following power and motion control appli- cations are supported by the pwm module: three-phase ac induction motor switched reluctance (sr) motor brushless dc (bldc) motor uninterruptable power supply (ups) 6.4.1 features overview the pwm module has the following features: up to 8 pwm i/o pins with 4 duty cycle genera- tors up to 16-bit resolution ? on-the-fly ? pwm frequency changes edge and center aligned output modes single-pulse generation mode interrupt support for asymmetrical updates in cen- ter-aligned mode. output override control for electrically commu- tated motor (ecm) operation ? special event ? comparator for scheduling other peripheral events a simplified block diagram of the pwm module is shown in figure 6-4. this module contains 4 duty cycle generators, num- bered 1 through 4. the module has 8 pwm output pins, numbered 0 through 7. the eight i/o pins are grouped into odd numbered/even numbered pairs. for comple- mentary loads, the even pwm pins must always be the complement of the corresponding odd i/o pin to pre- vent damage to the power transistor devices. conse- quently, the signals on the even numbered i/o pins have certain limitations when the module is in the com- plementary operating mode. 6.4.2 pwm timebase the pwm timebase is provided by a 16-bit timer with a prescaler and postscaler. the pwm timebase is config- ured via a special function register (sfr). the pwm timebase can be configured for four different modes of operation: free running mode single-shot mode continuous up/down count mode continuous up/down count mode with interrupts for double-updates. these four modes are selected by the ptmod1:ptmod0 bits in the ptcon sfr. the up/ down counting modes support center-aligned pwm generation. the single-shot mode allows the pwm module to support pulse control of certain electronically commutated motors (ecms). DSPIC30F ds70025d-page 22 advance information ? 2001 microchip technology inc. figure 6-4: pwm module block diagram (full module implementation) pdc4 pdc4 buffer output driver block pwmcon1 ptper buffer pwmcon2 ptper ptmr comparator comparator channel 4 dead time generator and override logic ptcon sevtcmp comparator special event trigger fltbcon ovdcon pwm enable and mode sfrs pwm manual control. channel 3 dead time generator and override logic channel 2 dead time generator and override logic pwm generator #3 pwm generator #2 pwm generator #4 sevtdir ptdir dtcon1 dead time control. special event postscaler flta pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm generator #1 channel 1 dead time generator and override logic fltb note : details of pwm generator #1, #2, and #3 not shown for clarity. internal 16-bit data bus pwm6 pwm7 dtcon2 fltacon fault pin control sfrs ? 2001 microchip technology inc. advance information ds70025d-page 23 DSPIC30F 6.5 qei module the quadrature encoder interface (qei) module is described below. the module provides the interface to incremental encoders for obtaining motor positioning data. incre- mental encoders are very useful and specific to motor control applications. figure 6-5 depicts a simplified block diagram of the qei module. figure 6-5: quadrature encoder module simplified block diagram 6.5.1 overview the quadrature encoder interface (qei) is a key fea- ture requirement for several motor control applications, such as switched reluctance (sr) motor and ac induction motor (acim). the operational features of the qei are, but not limited to: three input channels for two phase signals and index pulse 16-bit up/down position counter count direction status position measurement (x2 and x4) mode programmable digital noise filters on inputs alternate 16-bit timer/counter mode quadrature encoder interface interrupts quadrature decoder logic up/down 16-bit up/down counter qeb/updn qea/t5cki/ digital filter logic digital filter logic digital filter logic index clock dir clock divider t cy prescaler and sync. logic gate 1 0 tmr5cs t cy DSPIC30F ds70025d-page 24 advance information ? 2001 microchip technology inc. 6.6 input capture module this is a description of the input capture module and associated operational modes. input capture modules are useful in applications requiring frequency (period) and pulse measurement. 6.6.1 overview input capture is useful for such modes as: frequency/period/pulse measurements additional sources of external interrupts table 6-1 presents the timer resource allocation for the input capture module. table 6-1: suggested timer resource 6.6.2 input capture module operations the input capture module consists of four input cap- ture channels. the key operational features are: simple capture event mode timer2 and timer3 mode selection input capture during sleep mode interrupt on input capture event these operating modes are determined by setting the appropriate control and configuration bits. figure 6-6 depicts the input capture mode block diagram. figure 6-6: input capture mode block diagram 6.6.3 simple capture event mode the simple capture events are as follows: capture every falling edge capture every rising edge capture every 4th rising edge capture every 16th rising edge these simple input capture modes are configured by setting the appropriate control and configuration bits. functional mode timer resource input capture timer 2 and timer 3 capxbuf x 16 prescaler - 1, 4, 16 icx capxm2:capxm0 mode select 3 note 1: where ? x ? is shown reference is made to the registers or bits associated to the respective input capture channels 1 through n. 10 set flag and mode select pin capxif capxtmr timer2<15:0> timer3<15:0> from gp timer module ? 2001 microchip technology inc. advance information ds70025d-page 25 DSPIC30F 6.7 output compare/ pwm module this is a description of the output compare module and associated operational modes. the output com- pare module features are quite useful in applications requiring operational modes such as: generation of variable width output pulses power factor correction simple pwm operation the following section provides a basic description of the output compare/pwm module. table 6-2 presents the timer resource allocation. table 6-2: output compare suggested timer resource 6.7.1 output compare modularity the output compare module consists of 1 to ? n ? output compare channels with the following feature enhance- ments. the key operational features are, but not limited to: timer2 and timer3 selection mode simple output compare match mode dual output compare match mode simple glitchless pwm mode output compare during sleep mode interrupt on output compare/pwm event these operating modes are determined by setting the appropriate bits in output compare sfr (special function register). figure 6-7 depicts the output com- pare mode block diagram. cmprxm and cmprxs in the figure represent the dual compare registers. in the dual compare mode, the cmprxs register is used for the first compare and cmprxm is used for the second compare. when con- figured for the pwm mode of operation, the cmprxs is the slave latch (read-only) and cmprxm is the mas- ter latch. figure 6-7: output compare mode block diagram functional mode timer resource output compare 1 - n timer 2 or timer 3 cmprxs comparator output logic q s r cmpxm2:cmpxm0 output enable ocx/pwmx set flag bit cmpxif cmprxm mode select 3 note 1: where ? x ? is shown reference is made to the registers associated to the respective output com- pare channels 1, 2, 3 or 4. 0 1 pwmflt ocxtsel 0 1 t2p2_match t2<15:0> t3<15:0> t3p3_match from gp timer module DSPIC30F ds70025d-page 26 advance information ? 2001 microchip technology inc. 6.8 spi ? module 6.8.1 operating function description the serial peripheral interface (spi) module is a syn- chronous serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift reg- isters, display drivers, a/d converters, etc. this spi module includes all spi modes. a frame syn- chronization mode is also included for support of voice band codecs. the following sections describe the basic functionality of the spi module. figure 6-8 shows a block diagram of the spi. 6.8.2 serial peripheral interface (spi) spi mode is a high-speed serial i/o interface useful for communicating with peripheral devices (e.g., serial eeprom, serial a/d) and for i/o expansion. it is com- patible with motorola ? s spi ? and siop interfaces. the serial port consists of a 16-bit shift register, spisr, used for shifting data in and out, and a buffer register, spibuf. a control register, spicon, configures the module. additionally, a status register, spistat, indi- cates various status conditions. five pins make up the serial interface; sdi: serial data input; sdo: serial data output; sck: shift clock input or output, ss : active low slave select and fsync: frame synchronization pulse. in master mode operation, sck is clock output, but in slave mode, it is clock input. the control bit spien along with several control bits enables the serial port and configures sdi, sdo, sck and ss pins as serial port pins. a series of eight clock pulses shift out 8 bits from the spisr to sdo pin and simultaneously shift in 8-bit data from sdi pin. an interrupt is generated when the trans- fer is complete (interrupt flag bit spiif). this interrupt can be disabled through the interrupt enable bit spiie. the receive operation is double buffered. when a com- plete byte is received it is transferred from spisr to spibuf. transmit operation is not double buffered. the user writes directly to spisr. whereas a read operation will read spibuf, a write operation will write to both spisr and spibuf. in master mode, the clock is generated by prescaling the system clock. when an external clock source is used, a minimum high and low time must be observed. in master mode, data is transmitted as soon as spibuf is written. the interrupt is raised at the middle of the last bit duration (i.e., after the last bit in is latched). in slave mode, data is transmitted and received as external clock pulses appear on sck. again, the inter- rupt is set as the last bit is latched in. if ss control is enabled, then transmission and reception are enabled only when ss = low. sdo output will be disabled in ss mode with ss = high. 6.8.3 direction control of spi pins the input/output direction control on all the spi pins is controlled by the spi module. therefore, control sig- nals generated within the module will override the data direction control register on each spi pin based on the current operating mode of the module. the spi module can give up control of three pins. the ss pin is only controlled in slave mode with ss enabled. sdo has a control bit in spicon that allows the module to disable direction control, dissdo. fsync pin is only controlled when the frmen bit is high. ? 2001 microchip technology inc. advance information ds70025d-page 27 DSPIC30F figure 6-8: spi block diagram read write internal data bus sdi sdo ss sck spisr spibuf bit0 shift clock edge select f osc primary 1, 4, 16, 64 enable master clock prescaler secondary prescaler 1, 2, 3 ? 8 fsync ss & fsync control clock control DSPIC30F ds70025d-page 28 advance information ? 2001 microchip technology inc. 6.9 uart module this is the description of a universal asynchronous receiver/transmitter communications module. the uart module is defined closely to match the usart module from the pic18c family with a few key differ- ences. the dspic products will have one or more uart ? s. 6.9.1 overview of features the key features of the uart module are: full-duplex operation with 8- or 9-bit data even, odd or no parity options (for 8-bit data) one or two stop bits hardware flow control option with cts and rts pins fully integrated baud rate generator with 16-bit prescaler baud rates range from up to 2.5mbps and down to 38hz at 40mips 4-byte deep transmit data buffer 4-byte deep receive data buffer parity, framing and buffer overrun error detection 16x baud clock output for irda support support for interrupt only on address detect (9th bit=1) separate transmit and receive interrupts loopback mode for diagnostics 6.10 i 2 c ? module this document describes the inter-integrated circuit (i 2 c) function that offers full hardware support for both slave and multi-master modes, with a 16-bit interface. figure 6-9 shows an i 2 c receive block diagram and figure 6-10 shows an i 2 c transmit block diagram. 6.10.1 features overview inter-integrated circuit (i 2 c) interface i 2 c interface supports both master and slave modes. i 2 c slave mode supports 7- and 10-bit address. i 2 c master mode supports 7- and 10-bit address. i 2 c port allows bidirectional transfers between master and slaves. serial clock synchronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer. i 2 c supports multi-master mode. detects bus col- lision and will arbitrate accordingly. 6.10.2 operating function description the i 2 c module is a synchronous serial interface useful for communicating with other peripheral or microcon- troller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d convert- ers, etc. 6.10.3 inter-integrated circuit (i 2 c) the i 2 c module hardware fully implements all the mas- ter and slave functions of the i 2 c standard and fast mode specifications, as well as 7- and 10-bit address- ing. thus the i 2 c module can operate as a slave, or a mas- ter on an i 2 c bus. 6.10.4 various i 2 c modes there are no control bits to select a specific mode. however, all of the following modes are supported: i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c master mode (7- or 10-bit address) ? 2001 microchip technology inc. advance information ds70025d-page 29 DSPIC30F figure 6-9: i 2 c block diagram (i 2 c receive) figure 6-10: i 2 c block diagram (i 2 c transmit) 6.10.5 pin configuration in i 2 c mode in i 2 c mode, pin scl is clock and pin sda is data. the module will override the data direction bits for these pins. the pins that are used for i 2 c modes are config- ured as open-drain. 6.10.6 i 2 c registers i2ccon, and i2cstat are control and status registers, respectively. the i2ccon registers is readable and writable. the lower 6 bits of the i2cstat are read-only. the remaining bits of the i2cstat are read/write. i2crsr is the shift register used for shifting data in figure 6-9. i2crcv is the buffer register to which data bytes are written to or read from. this register is the receive buffer, as shown in figure 6-9. i2cxmt is the transmit register; bytes are written to this register during a trans- mit operation, as shown in figure 6-10. i2cadd register holds the slave address, and this reg- ister is now 10 bits wide to hold the full slave address. if 10-bit mode is desired, the 10-bit address preamble is recognized by the module, which then automatically enables 10-bit addressing mode. a status bit, add10, indicates 10-bit address mode. the i2cbrg acts as the baud rate generator reload value. the baud rate generator is a full baud rate generator. in receive operations, i2crsr and i2crcv together create a double buffered receiver. when i2crsr receives a complete byte, it is transferred to i2crcv and the i2c_int_flag interrupt is set. during transmis- sion, the i2ctrn is not double buffered. acknowledge generation read write i2crsr i2crcv internal data bus msb scl sda shift match detect i2cadd start and stop bit detect clock set, reset s, p bits addr_match (i2cstat reg) read write i2ctrn internal data bus msb scl sda shift clock DSPIC30F ds70025d-page 30 advance information ? 2001 microchip technology inc. 6.10.7 i 2 c 7-bit slave mode operation once enabled (i2cen = 1), the slave module will wait for a start bit to occur (idle_mode). following a start- bit detect, 8 bits are shifted into i2crsr and the address is compared against i2cadd. in 7-bit mode, bits i2cadd<6:0> are compared against bits i2crsr<7:1> and bit0 is the r/w bit. all incoming bits are sampled with the rising edge of scl. if the address matches, an acknowledge will be sent, and on the falling edge of the ninth bit (ack bit) the i2c_int_flag interrupt is set. 6.10.7.1 slave mode transmission if r/w bit received is a ? 1 ? then the serial port will go into ? xmit_mode ? . it will send ack on the ninth bit and then hold scl to ? 0 ? until the cpu responds by writing to i2ctrn. scl is released and 8 bits of data are shifted out. data bits are shifted out on the falling edge of scl such that sda is valid during scl high (see tim- ing diagram). interrupt is set on the falling edge of the ninth clock pulse. the ack bit from master is latched on the ninth clock pulse. if ack = 1 then ? xmit_mode ? ends and the serial port resumes ? idle_mode ? looking for another start bit. if ack = 0, then it will again hold scl low until i2ctrn is full (i.e., written to). tbf status flag : during transmit, the tbf bit (i2cstat<0>) is set when the cpu writes to i2ctrn, and tbf is cleared in hardware when all 8 bits are shifted out. iwcol status flag : if the user attempts to write a byte to the i2ctrn register when tbf = 1 (i.e., i2ctrn is still shifting out previous data byte), then iwcol is set. iwcol must be cleared in software. r/ w status flag : latches and holds the r/w bit received following the last address-match. 6.11 controller area network module (can) the controller area network (can) is a serial commu- nications protocol which efficiently supports distributed real-time control with a very high level of security. figure 6-11 shows a block diagram of a can module. the dsc can module satisfies the version 2.0b spec- ification, which allows message identifier lengths of 11 and/or 29 bits to be used (an identifier length of 29 bits allows over 536 million message identifiers). version 2.0b can is also referred to as "extended can". 6.11.1 can module features the can module is a communication controller imple- menting the can 2.0 a/b protocol as defined in the bosch specification. the module will support can 1.2, can 2.0a, can2.0b passive, and can 2.0b active versions of the protocol. the module implemen- tation is a full can system. based on requirements expressed by can application software authors for predictable real-time behavior and the need to mini- mize silicon and to save cost, the module implements an advanced buffer arrangement. note: following a restart condition in 10-bit mode, the user only needs to match the first 7-bit address. ? 2001 microchip technology inc. advance information ds70025d-page 31 DSPIC30F the module features are as follows: implementation of the can protocol standard and extended data frames 0 - 8 bytes data length programmable bit rate up to 1 mb/sec support for remote frames double buffered receiver with two prioritized received message storage buffers 6 full (standard/extended identifier) acceptance fil- ters, 2 associated with the high priority receive buffer, and 4 associated with the low priority receive buffer 2 full acceptance filter masks, one each associ- ated with the high and low priority receive buffers three transmit buffers with application-specified prioritization and abort capability programmable wake-up functionality with inte- grated low-pass filter programmable loop-back mode and programma- ble state clocking supports self-test operation signaling via interrupt capabilities for all can receiver and transmitter error states programmable clock source programmable link to timer module for time- stamping and network synchronization low power sleep mode figure 6-11: can module block diagram 3 tx buffers 2 rx buffers message assembly 6 acceptance filters cpu interface logic bit stream processor error management logic bit timing logic clock generator cpu bus int q clocks rx tx buffer DSPIC30F ds70025d-page 32 advance information ? 2001 microchip technology inc. 6.12 i/o pins some pins for the i/o pin functions are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. all i/o port pins have three registers directly associated with the operation of the port pin. the data direction register determines whether the pin is an input or an output. the port data latch register provides latched output data for the i/o pins. the port register provides visibility of the logic state of the i/o pins. reading the port register provides the i/o pin logic state, while writes to the port register write the data to the port data latch register. figure 6-12 illustrates a port/ lat/tris block diagram. figure 6-12: simplified block diagram of port/lat/tris operation 6.12.1 i/o pin features schmitt trigger input open drain output. ttl input levels cmos output drivers weak internal pull-up (gated) interrupt on change feature (inputs only) 6.12.2 i/0 port latch some i/o port pins have latch bits (latch register). the latch register when read will yield the contents of the i/o latch, and when written will modify the contents of the i/o latch, thus modifying the value driven out on a pin if the corresponding data direction register bit is configured for output. this can be used in read-modify- write instructions that allow the user to modify the con- tents of the latch register regardless of the status of the corresponding pins. q d ck wr lat + data latch i/o pin rd port wr port tris rd lat data bus ? 2001 microchip technology inc. ds70025d-page 33 ? all rights reserved. copyright ? 2001, microchip technology incorporated, usa. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no rep- resentation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accu- racy or use of such information, or infringement of patents or other intellectual property rights arising from such use or oth- erwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. no licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights. ? trademarks the microchip name, logo, pic, picmicro, picmaster, pic- start, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are registered trade- marks of microchip technology incorporated in the u.s.a. and other countries. total endurance, in-circuit serial programming (icsp), filter- lab, flexrom, fuzzylab, icepic, microid, mpasm, mplib, mplink, mxdev, picdem, picdem.net, dspic and migrat- able memory are trademarks of microchip technology incor- porated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2001, microchip technology incorporated, printed in the u.s.a., all rights reserved. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warrant y is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patent s or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and othe r countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds70025d-page 34 ? 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